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AMD lanza su sistema QuadCore: Barcelona

Esta es una discusión para el tema AMD lanza su sistema QuadCore: Barcelona en el foro Noticias y Novedades, bajo la categoría General; AMD lanzo el anuncio para su nuevo procesador Opteron en http://multicore.amd.com/us-en/quadcore/ este nuevo procesador sera lanzado en el nuevo socket ...
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  1. #1
    Banned
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    Predeterminado AMD lanza su sistema QuadCore: Barcelona

    AMD lanzo el anuncio para su nuevo procesador Opteron en http://multicore.amd.com/us-en/quadcore/

    este nuevo procesador sera lanzado en el nuevo socket F

    aca se detallan todas las mejoras:


    Quad-core
    - Native quad-core design
    - Redesigned and improved crossbar(northbridge)
    - Improved power management
    - New level of cache added, L3 VICTIM
    Power management - DICE(Dynamic Independent Core Engagement)
    - PLLs for each core, clocked independently and varies clock speed depending on usage.
    - ODMC power management: ability to shut down read channels if memory is only using writes and vice versa:
    * Reduces the power consumption of the memory controller by up to 80% on "many" workloads.
    - Aggressive grained clock gating
    - Power management state invariant time stamp counter (TSC)
    - Enhanced AMD's PowerNow - works independently without OS driver support
    Virtualization improvements
    - Nested Paging(NP):
    * Guest and Host page tables both exist in memory.(The CPU walks both page tables)
    * Nested walk can have up to 24 memory acesses! (Hardware caching accelerates the walk)
    * "Wire-to-wire" translations are cached in TLBs
    * NP eliminates Hypervisor cycles spent managing shadow pages(As much as 75% Hypervisor time)
    - Reduced world-switch time by 25%:
    * World-switch time: round-trup to Hypervisor and back
    Dedicated L1 cache
    - 256bit 128kB (64kB instruction/64kB data), 2-way associative
    - 2 x 128bit loads/cycle
    - lowest latency
    Dedicated L2 cache
    - 128bit 512kB, 16-way associative
    - 128bit bus to northbridge
    - reduced latency
    - eliminates conflicts common in shared caches - better for virtualization
    Shared L3 cache
    - 128bit 2MB, 32-way associative
    - Victim-cache architecture maximizes efficiency of cache hierarchy
    - Fills from L3 leave likely shared lines in the L3
    - Sharing-aware replacement policy
    - Expandable
    Independent DRAM controllers
    - Concurrency
    - More DRAM banks reduces page conflicts
    - Longer burst length improves command efficiency
    - Dual channel unbuffered 1066 support(applies to socket AM2+ and s1207+ QFX only)
    - Channel Interleaving
    Optimized DRAM paging
    - Increase page hits
    - Decrease page conflicts
    Re-architect northbridge for higher bandwidth
    - Increase buffer sizes
    - Optimize schedulers
    - Ready to support future DRAM technologies
    Write bursting
    - Minimize Rd/Wr Turnaround
    DRAM prefetcher
    - Track positive and negative, unit and non-unit strides
    - Dedicated buffer for prefetched data
    - Aggressively fill idle DRAM cycles
    Core prefetchers
    - DC Prefetcher fills directly to L1 Cache
    - IC Prefetcher more flexible
    * 2 outstanding requests to any address
    HyperTransport 3
    - Up to three 16bit cHT links
    - Up to 5200MT/s per link
    - Un-ganging mode: each 16bit HT link can be divided in two 8bit virutal links
    - Can dynamically adjust frequency and bit width to save power
    - AC mode (higher latency mode) to allow longer communications distances
    - Hot pluggable

    CPU Core IPC Enhancements:
    Advanced branch prediction
    - Dedicated 512-entry Indirect Predictor
    - Double return stacksize
    - More branch history bits and improved branch hashing
    History-based pattern predictor
    32B instruction fetch
    - Benefits integer code too
    - Reduced split-fetch instruction cases
    Sideband Stack Optimizer
    - Perform stack adjustments for PUSH/POP operations “on the side”
    - Stack adjustments don’t occupy functional unit bandwidth
    - Breaks serial dependence chains for consecutive PUSH/POPs
    Out-of-order load execution
    - New technology allows load instructions to bypass:
    * Other loads
    * Other stores which are known not to alias with the load
    - Significantly mitigates L2 cache latency
    TLB Optimisations
    - Support for 1G pages
    - 48bit physical address (256TB)
    - Larger TLBs key for:
    * Virtualized workloads
    * Large-footprint databases and
    * transaction processing
    - DTLB:
    * Fully-associative 48-way TLB (4K, 2M, 1G)
    * Backed by L2 TLBs: 512 x 4K, 128 x 2M
    - ITLB:
    * 16 x 2M entries
    Data-dependent divide latency
    Additional fastpath instructions
    – CALL and RET-Imm instructions
    – Data movement between FP & INT
    Bit Manipulation extensions
    - LZCNT/POPCNT
    SSE extensions
    - EXTRQ/INSERTQ (SSE4A)
    - MOVNTSD/MOVNTSS (SSE4A)
    - MWAIT/MONITOR (SSE3)
    Comprehensive Upgrades for SSE
    - Dual 128-bit SSE dataflow
    - Up to 4 dual precision FP OPS/cycle
    - Dual 128-bit loads per cycle
    - New vector code, SSE128
    - Can perform SSE MOVs in the FP “store” pipe
    - Execute two generic SSE ops + SSE MOV each cycle (+ two 128-bit SSE loads)
    - FP Scheduler can hold 36 Dedicated x 128-bit ops
    - SSE Unaligned Load-Execute mode:
    * Remove alignment requirements for SSE ld-op instructions
    * Eliminate awkward pairs of separate load and compute instructions
    * To improve instruction packing and decoding efficiency


    AMD empieza su campaña agresiva... y apunta directo al core2. esto solo va a terminar bien para los usuarios!!
    Última edición por jme; 22/03/2007 a las 23:44

  2. #2
    Senior Member Avatar de drunkie
    Fecha de ingreso
    09 may, 04
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    Términus
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    2,061

    Predeterminado

    AMD strikes back!!! Solo espero un bajon de precios por parte de Intel, dependiendo de ke tan bueno sea este micro.
    Amd fan :$
    Invisibility is for no purpose other than to be the greatest voyeur ever.
    Oh wai, I forgot ganks.

  3. #3
    Banned
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    27 mar, 04
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    Predeterminado



    el lanzamiento oficial sera en agosto... se suponia que iba a ser en junio, pero bueno...

    cuanto costara esta maravilla???

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